Nonvolatile memory device and method of fabricating the same

ABSTRACT

A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 2007-28001, filed on Mar. 22, 2007, Korean patent applicationnumber 2007-42979, filed on May 3, 2007, Korean patent applicationnumber 2007-63605, filed on Jun. 27, 2007, and Korean patent applicationnumber 2007-91555, filed on Sep. 10, 2007, which are incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a nonvolatile memory device and methodof fabricating the same.

In general, a memory cell of a nonvolatile memory device in which datais stored has a stacked gate structure. This stacked gate structure isformed by sequentially stacking a tunnel dielectric layer, a floatinggate, an inter-gate dielectric layer, a control gate and a gateelectrode layer over a channel region of the memory cell. The floatinggate is used as a charge trap layer and is generally formed of aconductive layer such as polysilicon.

Meanwhile, a nonvolatile memory device using a non-conductive layer (forexample, a nitride layer) as the charge trap layer instead ofpolysilicon has been proposed. The nonvolatile memory device using thenon-conductive layer as the charge trap layer, as described above, canbe classified into a SONOS (Silicon/Oxide/Nitride/Oxide/Silicon)nonvolatile memory device, a MANOS (Metal/Al₂O₃/Nitride/Oxide/Silicon)nonvolatile memory device, and so on depending on the material of a gateelectrode layer, etc. This nonvolatile memory device has a tunneldielectric layer forming a direct tunneling layer, a nitride layer forstoring charges, an insulating layer used as a blocking layer, and acontrol gate electrode.

In the nonvolatile memory device using a conductive layer, such aspolysilicon, as the charge trap layer, there is a problem that aretention time reduces significantly if any micro defect exists in thefloating gate. However, in the nonvolatile memory device using anon-conductive layer, such as a nitride layer, as the charge trap layer,there is an advantage in that sensitivity to defects in process isrelatively small due to the characteristic of the nitride layer.

Further, in the nonvolatile memory device using the conductive layer asthe charge trap layer, there are limitations to the implementation of alow-voltage operation and a high-speed operation because the tunneldielectric layer of about 70 angstroms or more in thickness is formedunder the floating gate. However, in the nonvolatile memory device usingthe non-conductive layer as the charge trap layer, a memory devicehaving a high-speed operation while requiring low voltage and low powercan be implemented because a relatively thin direct tunneling dielectriclayer is formed under the nitride layer.

In fabricating nonvolatile memory devices using the non-conductive layeras the charge trap layer, in general, isolation layers are formed in asemiconductor substrate through a STI (Shallow Trench Isolation) scheme,and a gate oxide layer, a nitride layer for storing charges, an oxidelayer used as a blocking layer, a gate electrode layer, and so on areformed over the semiconductor substrate including the isolation layers.A gate pattern process is then performed to thereby form a gateconstituting a memory cell.

However, if a flash memory device using this non-conductive layer as thecharge trap layer is fabricated, the nitride layers for storing chargesare not formed in respective memory cells separately, but areinterconnected in the direction of the memory cells even after the gatepattern process is carried out. In this case, charges trapped in thecharge trap layer included in a specific memory cell can diffuse intoneighboring memory cells in a horizontal direction as time goes by.

FIG. 1 is a sectional view illustrating a conventional method offabricating a MANOS type nonvolatile memory device.

Referring to FIG. 1, a semiconductor substrate 10 is etched to therebyform trenches. The trenches are gap-filled with an insulating layer,forming isolation layers 11. A tunnel dielectric layer 12 is then formedover an active region of the semiconductor device. A charge trap layer13, a blocking insulating layer 14, a metal electrode layer 15, and gateelectrode layers 16, 17 are sequentially formed over the entire surface.A gate pattern etch process is then performed to thereby form a gate ofa cell region.

In the conventional MANOS type nonvolatile memory device, the chargetrap layer 13 is also formed on an isolation region between activeregions. Thus, if baking is performed at high temperature afterprogramming is carried out by trapping charges in the charge trap layer13, the trapped charges move to neighboring gates, which may lower aprogram threshold voltage. It leads to a degraded retentioncharacteristic (i.e., the charge retention capability of a cell).

FIG. 2 is a sectional view illustrating a conventional method offabricating a SONOS type nonvolatile memory device.

Referring to FIG. 2, an isolation region of a semiconductor substrate 20is etched to thereby form isolation trenches. The trenches aregap-filled with an insulating layer, forming isolation layers 21. Atunnel dielectric layer 22, a charge trap layer 23, a blocking layer 24,a conductive layer 25 for a control gate, and a gate electrode layer 26are sequentially stacked over the entire surface including the isolationlayers 21.

In the conventional SONOS type nonvolatile memory device, a low voltagetransistor and a high voltage transistor are first formed in a periregion (i.e., a peripheral region), and a cell to be used as a storagemedium is then formed. In accordance with the above method, the chargetrap layer of the cell region is shared with neighboring cells in theword line direction. Due to this, a problem may arise because trappedcharges may move to neighboring gates, thereby lowering the programthreshold voltage of a cell. It leads to a degraded retentioncharacteristic (i.e., the charge retention capability of a cell).

Further, the charge trapping efficiency of the charge trap layer isabout 70% compared with that of the floating gate because not all thecharges passing through the tunnel dielectric layer are trapped, butonly part of them are trapped. In this case, the threshold voltagecorresponding to such short efficiency must be compensated for byincreasing a program bias, but it is very difficult to form a highvoltage transistor for transferring a high voltage.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to preventing charges, which arestored in a charge trap layer, from diffusing into neighboring memorycells by performing a patterning process on the charge trap layer inorder to form the charge trap layer only in each memory cell.

Further, the present invention is directed towards a method offabricating a nonvolatile memory device, which can improve the programthreshold voltage and thereby the retention characteristic of a cell, byforming charge trap layers in spaces between isolation layers formed inisolation regions of a semiconductor substrate in order to preventcharges, which are trapped in the charge trap layers, from moving toneighboring cell gates at the time of a program operation.

Furthermore, the present invention is directed towards a method offabricating a nonvolatile memory device, which can prevent charges,which are trapped in a charge trap layer, from moving to neighboringcell gates at the time of a program operation and, thereby improve theprogram threshold voltage and retention characteristic of a cell, byforming the charge trap layer over a semiconductor substrate and thenforming isolation layers through a subsequent process in order toelectrically isolate charge trap layers of memory cells from those ofother memory cells adjacent in the direction of bit lines through theisolation layers.

In accordance with an aspect of the present invention, there is provideda method of fabricating a nonvolatile memory device, including forming afirst dielectric layer on a semiconductor substrate in which activeregions are defined by isolation layers, forming a charge trap layer onthe first dielectric layer, removing the first dielectric layer and thecharge trap layer over the isolation layers, forming a second dielectriclayer on the isolation layers including the charge trap layer, andforming a conductive layer on the second dielectric layer.

The charge trap layer may be formed on the active regions and at edgeportions of the isolation layers.

The charge trap layer may be formed only on the active regions. Theformation of the isolation layers in the semiconductor substrate mayinclude forming a pad nitride layer on the semiconductor substrate,forming first mask patterns on the pad nitride layer having open regionscorresponding to the isolation layers, patterning the pad nitride layerusing the first mask patterns and forming trenches in the semiconductorsubstrate, and gap-filling the trenches with an insulating material,thus forming the isolation layers. When the charge trap layer and thefirst dielectric layer are patterned, second mask patterns having openregions may be formed on the charge trap layer. The first mask patternsmay have open regions identical to or wider than those of the secondmask patterns.

The charge trap layer may be formed of insulating material such as anitride layer.

In accordance with another aspect of the present invention, there isprovided a nonvolatile memory device, including a semiconductorsubstrate in which active regions are defined by isolation layers, firstdielectric layers isolated from each other and formed in the activeregions, respectively, a charge trap layer formed of insulating materialand formed only on the first dielectric layer, a second dielectric layerformed on the semiconductor substrate and the charge trap layer, and aconductive layer formed on the second dielectric layer.

The first dielectric layer may be partially formed on the isolationlayers.

In accordance with still another aspect of the present invention, thereis provided a method of fabricating a nonvolatile memory device,including forming an insulating layer and a hard mask layer over asemiconductor substrate, forming trenches by etching an isolation regionof the semiconductor substrate through an etch process employing thehard mask layer and gap-filling the trenches with an insulating layer,thus forming isolation layers, forming a passivation dielectric layer onthe insulating layer for the hard mask including the isolation layers,etching and removing the passivation dielectric layer, the hard masklayer and the insulating layer thereby forming protruded isolationlayers, sequentially stacking a tunnel dielectric layer, a charge traplayer and a buffer dielectric layer on the entire surface of thesemiconductor substrate including the isolation layers, and performing apolishing process to expose a top surface of the protruded isolationlayers, so the tunnel dielectric layer and the charge trap layer remainon active regions of the semiconductor substrate.

After the polishing process, a blocking insulating layer, a metal layerand a gate electrode layer on the entire surface including the isolationlayers may be sequentially stacked.

The passivation dielectric layer may be formed of a nitride layer of 200to 4000 angstroms in thickness using a LP-CVD or PE-CVD method. Aprotruding height of the isolation layer may be in the range of 200 to800 angstroms.

The tunnel dielectric layer may be formed by a thermal dry oxidizationprocess, a thermal we oxidization process or a radical oxidizationprocess. A height of the charge trap layer may be lower than that of atop surface of the isolation layer.

The charge trap layer may be formed of stoichiometric silicon nitride orSi-rich nitride to a thickness of 40 to 200 angstrom by a LP-CVD orPE-CVD method.

The buffer dielectric layer may be formed of HDP (High Density Plasma)oxide, SOG (Spin On Glass), USG (Undoped Silicate Glass, PSG(PhosphoSilicate Glass) or BPSG (BoroPhosphoSilicate Glass) to athickness of 500 to 4000 angstroms.

In accordance with still another aspect of the present invention, thereis provided a method of fabricating a nonvolatile memory device,including a method of fabricating a nonvolatile memory device, includingsequentially stacking a first tunnel dielectric layer, a charge traplayer, a blocking insulating layer and a first conductive layer on asemiconductor substrate in which a cell region and a peri region aredefined, forming isolation trenches by etching the first conductivelayer, the blocking insulating layer, the charge trap layer, the firsttunnel dielectric layer and the semiconductor substrate, formingisolation layers by gap-filling the isolation trenches with aninsulating layer, and sequentially forming a second conductive layer anda metal gate layer on the entire surface including the first conductivelayer.

The method further includes, before the second conductive layer isformed after the isolation layers are formed, forming a passivationdielectric layer in the cell region, removing the first conductivelayer, the blocking insulating layer, the charge trap layer and thefirst tunnel dielectric layer formed in the peri region, controlling aheight of the isolation layers by etching a protruding top surface ofthe isolation layers formed in the peri region, forming a second tunneldielectric layer for a transistor over the exposed semiconductorsubstrate of the peri region, and removing the passivation dielectriclayer.

The tunnel dielectric layer may be formed of an oxide layer to athickness of 10 to 100 angstroms. The charge trap layer may have a mixedlayer of a nitride layer or an oxide layer and a nitride layer and maybe formed to a thickness of 10 to 100 angstroms. The blocking insulatinglayer may have a dual structure of an oxide layer, a nitride layer or anoxide layer and a nitride layer and may be formed to a thickness of 10to 500 angstroms. The first and second conductive layers for the controlgate may be formed of a polysilicon layer.

After the first conductive layer is formed, an impurity may be furtherimplanted into the charge trap layer by performing an ion implantationprocess before the isolation trenches are formed. The ion implantationprocess may be performed using As or P as the impurity.

The passivation dielectric layer may be formed of a nitride layer.

The tunnel dielectric layer for the transistor may be formed to athickness of 100 to 600 angstroms in the case of a high voltagetransistor, and the tunnel dielectric layer for the transistor may beformed to a thickness of 100 to 200 angstroms in the case of a lowvoltage transistor.

The charge trap layer may have a mixed layer of a nitride layer or anoxide layer and a nitride layer. The charge trap layer may be formed ofHFO₂, ZrO₂, HFAlO, HFSiO, ZrAlO or ZrSiO.

After the blocking insulating layer is formed, a RTP (Rapid ThermalProcessing) may be performed in order to improve a film quality of theblocking insulating layer.

The first conductive layer and the second conductive layer may be formedof a polysilicon layer or a metal layer. The polysilicon layer may beformed of a polysilicon layer doped with an N⁺ impurity. The ion dopingconcentration of the impurity may range from 1E19 atoms/cm³ to 5E20atoms/cm³. The metal layer may be formed of TaN.

In accordance with further still another aspect of the presentinvention, there is provided a nonvolatile memory device, including atunnel dielectric layer, a charge trap layer, a blocking insulatinglayer and a first conductive layer sequentially stacked on asemiconductor substrate, isolation layers protruding as high as a heightof the first conductive layer in isolation regions of the semiconductorsubstrate and configured to isolate the tunnel dielectric layer, thecharge trap layer, the blocking insulating layer and the firstconductive layer from a neighboring tunnel dielectric layer, aneighboring charge trap layer, a neighboring blocking insulating layerand a neighboring first conductive layer, and a second conductive layerand a metal gate layer sequentially stacked on the isolation layers andthe first conductive layer.

The charge trap layer may be formed of a nitride layer or a mixed layerof an oxide layer and a nitride layer. The charge trap layer may beformed of HFO₂, ZrO₂, HFAlO, HFSiO, ZrAlO or ZrSiO.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view illustrating a conventional method offabricating a MANOS type nonvolatile memory device;

FIG. 2 is a sectional view illustrating a conventional method offabricating a SONOS type nonvolatile memory device;

FIGS. 3A to 3F are sectional views illustrating a method of fabricatinga nonvolatile memory device in accordance with a first embodiment of thepresent invention;

FIGS. 4A to 4G are sectional views illustrating a method of fabricatinga nonvolatile memory device in accordance with a second embodiment ofthe present invention; and

FIGS. 5A to 5E are sectional views illustrating a method of fabricatinga nonvolatile memory device in accordance with a third embodiment of thepresent invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Now, specific embodiments according to the present invention will bedescribed with reference to the accompanying drawings. However, thepresent invention is not limited to the disclosed embodiments, but maybe implemented in various manners. The embodiments are provided tocomplete the disclosure of the present invention and to allow thosehaving ordinary skill in the art to understand the scope of the presentinvention. The present invention is defined by the category of theclaims.

FIGS. 3A to 3F are sectional views illustrating a method of fabricatinga nonvolatile memory device in accordance with a first embodiment of thepresent invention.

Referring to FIG. 3A, a screen oxide layer (not shown) is formed on asemiconductor substrate 300. The screen oxide layer functions to preventdamage to the surface of the semiconductor substrate 300 in subsequentprocesses such as a well ion implantation process or a threshold voltageion implantation process. Subsequently, the well ion implantationprocess is performed so as to form a well region in the semiconductorsubstrate 300 and the threshold voltage ion implantation process isperformed so as to control the threshold voltage of a semiconductorelement such as a transistor. The well region (not shown) is formed inthe semiconductor substrate 300 and can have a triple structure.

After the screen oxide layer is removed, a pad nitride layer 302 isformed on the semiconductor substrate 300. Then, first mask patterns 304are formed over the pad nitride layer 302. The first mask patterns 304have open regions corresponding to trenches which are formed in thesemiconductor substrate 300 in a subsequent process. An oxide layer (notshown) having an etch selectivity different from that of the pad nitridelayer 302 may be further formed between the pad nitride layer 302 andthe first mask patterns 304. The oxide layer (not shown) can function toprevent damage to the surface of the semiconductor substrate 300 in asubsequent etch process.

Referring to FIG. 3B, the pad nitride layer 302 (refer to FIG. 3A) ispatterned by an etch process employing the first mask patterns 304(refer to FIG. 3A) as an etch mask. Trenches are then formed in thesemiconductor substrate 300. Insulating material is formed on the firstmask patterns 304 (refer to FIG. 3A) including the trenches, so thetrenches are gap-filled with the insulating material. The insulatingmaterial, the first mask patterns 304 (refer to FIG. 3A) and the padnitride layer 302 (refer to FIG. 3A) formed over the semiconductorsubstrate 300 are removed by performing a polishing process, such as aCMP (Chemical Mechanical Polishing) process, on the semiconductorsubstrate 300. Consequently, the insulating material remains only in thetrenches formed in the semiconductor substrate 300, thereby formingisolation layers 306. A plurality of active regions (not shown) are alsodefined by the isolation layers 306 in the semiconductor substrate 300.

Referring to FIG. 3C, a first dielectric layer 308 is formed on thesemiconductor substrate 300 including the isolation layers 306. Thefirst dielectric layer 308 may serve as a tunnel dielectric layer in anonvolatile memory device using a non-conductive layer as a charge traplayer. A charge trap layer 310 is formed on the first dielectric layer308, subsequently. The charge trap layer 310 is formed over the entireupper surface of the semiconductor substrate 300 over the plurality ofactive regions defined by the isolation layers 306. The charge traplayer 310 may be a non-conductive layer such as a nitride layer.

A buffer layer 312 is formed on the charge trap layer 310. The bufferlayer 312 can function to prevent damage to the charge trap layer 310during a subsequent etch process. Second mask patterns 314 are formed onthe buffer layer 312, subsequently. The second mask patterns 312 haveopen regions corresponding to the isolation layers 306 formed in thesemiconductor substrate 300. The open regions of the second maskpatterns 312 may be much smaller than those of the first mask patterns304. Meanwhile, although not shown in the drawings, the second maskpatterns 314 may be formed in the same manner as the first mask patterns304 formed in the previous process. In this case, there is an advantagein that a photomask which is used to form the first mask patterns 304can be used to form the second mask patterns 314 without change.

Referring to FIG. 3D, the buffer layer 312, the charge trap layer 310and the first dielectric layer 308 formed under the second mask patterns314 are patterned by performing an etch process employing the secondmask patterns 314 as an etch mask. Thus, the charge trap layer 310disposed in the open regions of the second mask patterns 314 is removed.The charge trap layer 310, which was formed to be connected horizontallyover the plurality of active regions, is disconnected and isolated onthe active region. Here, an edge portion of the charge trap layer 310 isadjusted to a boundary portion of the isolation layer 306. However, ifthe open region of the second mask pattern 314 is much smaller than thatof the first mask pattern 304, the width of the charge trap layer 310remaining after the etch process employing the second mask patterns 314is further widened, so that a part of the disconnected charge trap layer310 may exist on the isolation layers 306. In this case, the amount ofcharges stored in the charge trap layer 310 can be increased, therebyimproving the device characteristics. Meanwhile, if the open regions ofthe second mask pattern 314 are identical to those of the first maskpattern 304, the charge trap layer 310 may not exist on the isolationlayers 306, but may be formed only on the active region.

Conventionally, the charge trap layers 310 are formed horizontally overthe plurality of active regions and remain connected in a horizontaldirection over a number of memory cells even after a subsequent gateetch process. In this case, charges stored in the charge trap layer 310included in a specific memory cell may diffuse horizontally as time goesby, thereby causing a shift in the threshold voltage because of apotential difference. This may degrade the data retention characteristicof the memory cell. This problem will emerge as a problem that must beconsidered seriously as the size of a memory cell gradually decreases.

As described above, in accordance with the present invention, the chargetrap layers 310 are isolated from one another so that they are formedonly in the active regions, respectively. Thus, the charge trap layers310 can be isolated from one anther and formed only in respective memorycells formed through a subsequent process. Accordingly, it can reducethe occurrence of problems such as potential drop, a shift in thethreshold voltage and degradation of the data retention characteristic,which are generated when charges stored in the charge trap layers 310move to neighboring memory cells.

Referring to FIG. 3E, the second mask patterns 314 (refer to FIG. 3D)and the buffer layer 312 (refer to FIG. 3D) formed over thesemiconductor substrate 300 are removed.

Referring to FIG. 3F, a second dielectric layer 316 is formed over thesemiconductor substrate 300 including the isolation layers 306 and thecharge trap layers 310. The second dielectric layer 316 can be formedwhile maintaining a step formed by the first dielectric layer 308 andthe charge trap layer 310 stacked over the semiconductor substrate 300.The second dielectric layer 316 may be formed of an oxide layer such asAl₂O₃. At this time, charges stored in the charge trap layer 310 cannotmove to neighboring charge trap layers 310 due to the energy barrierexisting between the charge trap layer 310 and the second dielectriclayer 316. A conductive layer 318 is formed on the second dielectriclayer 316 subsequently. The conductive layer 318 may be formed of ametal layer. Although not shown in the drawings, the process of forminga memory cell including the charge trap layers 310, which are isolatedfrom one another, is completed by patterning the stacked layers througha gate etch process.

FIGS. 4A to 4G are sectional views illustrating a method of fabricatinga nonvolatile memory device in accordance with a second embodiment ofthe present invention.

Referring to FIG. 4A, a capping dielectric layer 401, an insulatinglayer 402 for forming isolation layers, and a hard mask layer 403 aresequentially formed over a semiconductor substrate 400. The cappingdielectric layer 401 may be formed of an oxide layer. The sum of thethickness of the capping dielectric layer 401, the insulating layer 402and the hard mask layer 403 may be in the range of 500 to 4000angstroms. The insulating layer 402 may be formed of a nitride layer.Subsequently, photoresist patterns 404 for forming isolation trenchesare formed by exposure and development processes.

Referring to FIG. 4B, the hard mask layer 403, the insulating layer 402,and the capping dielectric layer 401 are sequentially etched andpatterned by an etch process employing the photoresist patterns 404 asan etch mask. The exposed semiconductor substrate 400 is etched tothereby form trenches 405. The trenches 405 may be formed to a depth of1500 to 2500 angstroms by etching the semiconductor substrate 400.

Referring to FIG. 4C, after the photoresist patterns are removed by astrip process, an insulating layer is deposited over the entire surface.A CMP process is then performed so that the hard mask layer 403 isexposed, thus forming isolation layers 406 within the trenches 405. Theisolation layers 406 may be formed of an HDP (High Density Plasma) oxidelayer, an SOG (Spin On Glass) oxide layer, USG (Undoped Silicate Glass,PSG (PhosphoSilicate Glass) or BPSG (BoroPhosphoSilicate Glass). Apassivation dielectric layer 407 is formed over the entire surfaceincluding the isolation layers 406, subsequently. The passivationdielectric layer 407 functions to prevent a top surface of the isolationlayers 406 from being lost in a subsequent etch process. The passivationdielectric layer 407 may be formed of a nitride layer to a thickness of200 to 4000 angstroms using a LP-CVD or PE-CVD method.

Referring to FIG. 4D, the passivation dielectric layer 407, the hardmask layer 403, the insulating layer 402, and the capping dielectriclayer 401, which are formed over the active regions, are sequentiallyremoved by performing an etch process. The isolation layer 406 has aprotrusion projecting upwardly from the semiconductor substrate 400. Theheight of the protrusion may range from 200 to 800 angstroms. Here, thepassivation dielectric layer 407, the hard mask layer 403 and theinsulating layer 402 may be removed by a we etch process employingH₂PO₄. Alternatively, the passivation dielectric layer 407, the hardmask layer 403 and the insulating layer 402 may be removed by a dry etchprocess.

Referring to FIG. 4E, a tunnel dielectric layer 408 is formed on theactive regions of the semiconductor substrate 400. That is, the tunneldielectric layer 408 is formed in regions between the isolation layers406. The tunnel dielectric layer 408 may be formed by a thermal dryoxidization process, a thermal we oxidization process or a radicaloxidization process. A charge trap layer 409 is then formed over theentire surface including the tunnel dielectric layer 408. Here, thethickness of the charge trap layer 409 formed on the active region canbe lower than that of the charge trap layer 409 formed on a top surfaceof the isolation layers 406. The charge trap layer 409 may be formed toa thickness of 40 to 200 angstroms by a LP-CVD or PE-CVD method. Thecharge trap layer 409 may be formed of stoichiometric silicon nitride orSi-rich nitride. A buffer dielectric layer 410 is then formed over theentire surface. The buffer dielectric layer 410 may be formed of HDPoxide, SOG, USG, PSG or BPSG to a thickness of 500 to 4000 angstroms.

Referring to FIG. 4F, a CMP process is performed until the top surfaceof the isolation layer 406 is exposed. Thus, the charge trap layer 409formed on the top surface of the isolation layer 406 is removed so thatthe charge trap layer 409 remains only on the active regions.

Referring to FIG. 4G, a blocking insulating layer 411, a metal layer412, a first gate electrode layer 413 and a second gate electrode layer414 are sequentially stacked over the entire surface including theisolation layers 406. A patterning process is then performed to therebyform a gate of a cell region. The blocking insulating layer 411 may beformed of SiO₂ (silicon oxide), Al₂O₃ (alumina) (i.e., a high-kmaterial), Ta₂O₅ (tantalum oxide), ZrO₃ (zirconium oxide), HfO₂ (hafniumoxide), La₂O₃ (lanthanum oxide), TiO₂ (titanium oxide), SrTiO₃(strontium oxide titanite oxide), a combination thereof, or oxide andferroelectric material of the perovskite structure. The metal layer 412may be formed of TiN, TiCN, TaN or TaCN. Each of the blocking insulatinglayer 411 and the metal layer 412 may be formed by a CVD (Chemical VaporDeposition), PVD (Physical Vapor Deposition) or ALD (Atomic LayerDeposition) method. The first gate electrode layer 413 may be formed ofpolysilicon and the second gate electrode layer may be formed of WSix.

FIGS. 5A to 5E are sectional views illustrating a method of fabricatinga nonvolatile memory device in accordance with a third embodiment of thepresent invention.

Referring to FIG. 5A, a first tunnel dielectric layer 501 and a chargetrap layer 502 are sequentially formed over a semiconductor substrate500. The first tunnel dielectric layer 501 may be formed of an oxidelayer to a thickness of 10 to 500 angstroms using a radical oxidizationmethod or a thermal oxidization method. The charge trap layer 502 may beformed of a nitride layer. The charge trap layer 502 may be formed by anALD or CVD method. The charge trap layer 502 may be formed of aLP-nitride layer or PE-nitride layer to a thickness of 10 to 500angstroms. The charge trap layer 502 may be formed of a mixed layer ofan oxide layer and a nitride layer instead of the nitride layer. Thecharge trap layer 502 may also be formed of HFO₂, ZrO₂, HFAlO, HFSiO,ZrAlO or ZrSiO.

A blocking insulating layer 503 and a first conductive layer 504 aresequentially stacked, subsequently. The blocking insulating layer 503may be formed of an oxide layer. The blocking insulating layer 503 mayalso be formed of hafnium oxide, aluminum oxide or zirconium oxide.Alternatively, the blocking insulating layer 503 may be formed of anitride layer instead of the oxide layer. Alternatively, the blockinginsulating layer 503 may have a dual structure of an oxide layer and anitride layer. The blocking insulating layer 503 may be formed to athickness of 10 to 500 angstroms. After the blocking insulating layer503 is formed, a RTP (Rapid Thermal Processing) may be performed so asto improve the film quality of the blocking insulating layer 503.

The first conductive layer 504 may be formed of a polysilicon layer or ametal layer. The polysilicon layer may be formed of a polysilicon layerdoped with an N⁺ impurity. In this case, the ion doping concentration ofthe polysilicon layer may range from 1E19 atoms/cm³ to 5E20 atoms/cnn³.A TaN layer can be used as the metal layer to form the first conductivelayer 504.

Thereafter, to increase a possible number of traps of the charge traplayer 502, an ion implantation process is carried out. The ionimplantation process is performed by implanting As or P as an impurity.A hard mask layer 505 is then formed on the first conductive layer 504.

Referring to FIG. 5B, the semiconductor substrate 500 is exposed bysequentially etching the hard mask layer 505, the first conductive layer504, the blocking insulating layer 503, the charge trap layer 502 andthe first tunnel oxide layer 501 formed over an isolation region of acell region (i.e., a memory cell region). The exposed semiconductorsubstrate 500 is etched to thereby form trenches 506 a in the cellregions. In a similar way, a trench 506 b is formed in an isolationregion of a peri region (i.e., a peripheral region). The trench 506 a ofthe cell region and the trench 506 b of the peri region can be formedseparately or simultaneously.

Insulating layers 507 for element isolation are formed over the entiresurface including the trench 506 a, 506 b. The insulating layer 507 maybe formed of an SOG, SOD or HDP oxide layer.

The formation process of the trench 506 a of the cell region and thetrench 506 b of the peri region, and the formation process of theinsulating layer 507 may be performed anterior to the formation of thefirst conductive layer 504 after the blocking insulating layer 503 isformed.

Referring to FIG. 5C, a polishing process is performed until the firstconductive layer 504 is exposed. Preferably, a CMP process may beperformed in order to form the isolation layers 507. In case that theformation process of the trench 506 a of the cell region and the trench506 b of the peri region, and the formation process of the insulatinglayer 507 are performed after the blocking insulating layer 503 isformed without forming the first conductive layer 504, a polishingprocess is preferably performed until the blocking insulating layer 503is exposed.

Thus, the charge trap layer 502 is electrically insulated from aneighboring charge trap layer 502 in a bit line direction by means ofthe isolation layer 507. It prevents trapped charges from moving to aneighboring cell.

A passivation dielectric layer 508 is formed over the entire surfaceincluding the isolation layers 507. The passivation dielectric layer 508may be formed of a nitride layer. An etch process is then preformed tothereby remove the passivation dielectric layer 508 formed on the periregion.

Referring to FIG. 5D, the semiconductor substrate 500 is exposed bysequentially etching the first conductive layer 504, the blockinginsulating layer 503, the charge trap layer 502, and the first tunneldielectric layer 501 exposed over the peri region. Here, the firsttunnel dielectric layer 501 may not be removed and remain in order toform it into a second tunnel dielectric layer through control of itsthickness in a subsequent oxidization process. Thereafter, a protrudedtop surface of the isolation layer 507 is etched so as to control theheight of the isolation layer 507. An oxidization process is thenperformed to thereby form a second tunnel dielectric layer 509 on theexposed semiconductor substrate 500. The second tunnel dielectric layer509 may be formed of an oxide layer. When a transistor to be formed inthe peri region is a low voltage transistor, the second tunneldielectric layer 509 may be formed to a thickness of 500 to 200angstroms, and when the transistor to be formed in the peri region is ahigh voltage transistor, the second tunnel dielectric layer 509 may beformed to a thickness of 500 to 600 angstroms.

As described above, after the passivation dielectric layer 508 is formedin the cell region, the tunnel dielectric layer for a high voltage canbe formed in the peri region. Accordingly, a high voltage transistor canbe formed easily.

An etch process is then performed so as to remove the passivationdielectric layer 508 formed in the memory cell region.

Referring to FIG. 5E, a second conductive layer 510 is formed over theentire surface including the first conductive layers 504 formed in thecell regions and the second tunnel dielectric layers 509 formed in theperi region. The second conductive layer 510 may be formed using thesame material as the first conductive layer 504. To reduce resistivityof a gate electrode, a metal gate layer 511 is formed on the secondconductive layer 510. The metal gate layer 511 may be formed of WSi orWN/WSi when the first conductive layer 504 and the second conductivelayer 510 are formed of a polysilicon layer. Alternatively, the metalgate layer 511 may be formed of polysilicon/WN/WSi when the firstconductive layer 504 and the second conductive layer 510 are formed of ametal layer.

It is to be understood that the above embodiments of the presentinvention may also be applied to TANOS(Tantalum/Al₂O₃/Nitride/Oxide/Silicon) type nonvolatile memory devicesas well as the SONOS and MANOS type nonvolatile memory devices.

In accordance with the first embodiment of the present invention, thecharge trap layer is formed in each memory cell by performing apatterning process on the charge trap layer. Charges stored in thecharge trap layer can be prevented from diffusing into neighboringmemory cells. Accordingly, it can reduce the occurrence of problems suchas potential drop, a shift in the threshold voltage, and degradation ofthe data retention characteristic, etc., which are generated whencharges stored in the charge trap layer move to neighboring memorycells.

In accordance with the second embodiment of the present invention, thecharge trap layers are formed in the spaces between the isolation layersformed in the isolation regions of the semiconductor substrate. It canprevent charges, which are trapped in the charge trap layer, from movingto neighboring cell gates at the time of a program operation.Accordingly, the program threshold voltage and, thereby, the retentioncharacteristic of a cell can be improved.

In accordance with the third embodiment of the present invention, thecharge trap layer is formed over the semiconductor substrate before theisolation layers are formed by a subsequent process. The charge traplayer of a memory cell is electrically isolated from the charge traplayers of neighboring memory cells in the bit line direction by means ofthe isolation layers. It can prevent charges, which are trapped in thecharge trap layer, from moving to neighboring cell gates at the time ofa program operation. Accordingly, the program threshold voltage and,thereby, the retention characteristic of a cell can be improved.Further, after the passivation dielectric layer is formed in the cellregion, the tunnel dielectric layer for a high voltage transistor or alow voltage transistor is formed in the peri region by controlling thethickness of the tunnel dielectric layer. Accordingly, a high voltagetransistor or a low voltage transistor can be formed easily.

The embodiments disclosed herein have been proposed to allow a personskilled in the art to easily implement the present invention, and theperson skilled in the part may implement the present invention by acombination of these embodiments. Therefore, the scope of the presentinvention is not limited by or to the embodiments as described above,and should be construed to be defined only by the appended claims andtheir equivalents.

1-30. (canceled)
 31. A nonvolatile memory device, comprising: a tunneldielectric layer, a charge trap layer, a blocking insulating layer and afirst conductive layer sequentially stacked on a semiconductorsubstrate; isolation layers protruding as high as a height of the firstconductive layer in isolation regions of the semiconductor substrate andconfigured to isolate the tunnel dielectric layer, the charge traplayer, the blocking insulating layer and the first conductive layer froma neighboring tunnel dielectric layer, a neighboring charge trap layer,a neighboring blocking insulating layer and a neighboring firstconductive layer; and a second conductive layer and a metal gate layersequentially stacked on the isolation layers and the first conductivelayer.
 32. The nonvolatile memory device of claim 31, furthercomprising: an insulating layer for a transistor formed in a peripheralregion of the semiconductor substrate; an isolation layer protruding ashigh as a height of the insulating layer for the transistor in theperipheral region of the semiconductor substrate and configured toisolate the insulating layer for the transistor from neighboringinsulating layers for a transistor; and the first conductive layer andthe second conductive layer sequentially stacked on the isolation layerand the insulating layer for the transistor, of the peripheral region.33. The nonvolatile memory device of claim 31, wherein the charge traplayer is formed of a nitride layer or a mixed layer of an oxide layerand a nitride layer.
 34. The nonvolatile memory device of claim 31,wherein the charge trap layer is formed of HFO2, ZrO2, HFAlO, HFSiO,ZrAlO or ZrSiO.
 35. The nonvolatile memory device of claim 31, whereinthe charge trap layer is formed to a thickness of 40 to 200 angstroms.36. The nonvolatile memory device of claim 31, wherein the blockinginsulating layer is formed of hafnium oxide, aluminum oxide or zirconiumoxide.
 37. The nonvolatile memory device of claim 31, wherein the firstconductive layer is formed of a polysilicon layer or a metal layer. 38.The nonvolatile memory device of claim 38, wherein the polysilicon layeris formed of a polysilicon layer doped with a N+ impurity.
 39. Thenonvolatile memory device of claim 38, wherein the metal layer is formedof TaN layer.
 40. The nonvolatile memory device of claim 32, wherein theinsulating layer for the transistor is formed to a thickness of 500 to600 angstroms in the case of a high voltage transistor, and theinsulating layer for the transistor is formed to a thickness of 200 to500 angstroms in the case of a low voltage transistor.